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01 · THE FULL SYSTEM

3072 virtual antennas. One coherent aperture.

Eight subarray boards with sixteen data AWR2243 plus two cascade LO masters form a 48 TX × 64 RX array — 3072 cross-coherent virtual antennas, streamed as raw IQ into a Jetson AGX Orin in under 30 ms end to end.

16+2
AWR2243 MMICS
48×64
TX × RX
3072
VIRTUAL ANTENNAS
8
SUBARRAYS
<30 ms
END-TO-END LATENCY
02 · TOPOLOGY

Eight boards. Eight links. One Jetson.

Every subarray board sends exactly one A-PHY long-reach link; eight links land at the Valens deserializers, cross to C-PHY and appear as sixteen plain V4L2 devices.

CONTROL FRONTEND · 8× SUBARRAY BOARD A-PHY · 8× CABLE ~15 m · 4.6 GBIT/S PER LINK DES → C-PHY JETSON · V4L2 Cascade-Master A MASTER-MASTER · AWR2243 LO → ALL 8 SUB Cascade-Master B MASTER-SLAVE · AWR2243 LO → ≤ 4 SUB (ALT.) 8× STM32L5 1 PER SUBARRAY · SPI · I²C SUBARRAY COHERENCE 8 / 0 · ALL COHERENT 7 / 1 · 7 + 1 AUTONOMOUS 4 / 3 / 1 · SPLIT + AUTONOMOUS SUBARRAY 1 6T × 8R · 48 ANT AWR-1a AWR-1b COMB2→1 · 2 VC SER · VA70xxA-PHY OUT SUBARRAY 2 6T × 8R · 48 ANT AWR-2a AWR-2b COMB2→1 · 2 VC SER · VA70xxA-PHY OUT × 4 MORE SUBARRAYS SAME SCHEME · → VIDEO4..11 SUBARRAY 7 6T × 8R · 48 ANT AWR-7a AWR-7b COMB2→1 · 2 VC SER · VA70xxA-PHY OUT SUBARRAY 8 6T × 8R · 48 ANT AWR-8a AWR-8b COMB2→1 · 2 VC SER · VA70xxA-PHY OUT Σ 8 LINKS VALENS DES BANK 8× A-PHY IN FEC · 16 VCs → C-PHY OUT 4× C-PHY TRIOS JETSON AGX ORIN · USERSPACE V4L2 /dev/video0 .. 15 16 STREAMS · MMAP · ZERO-COPY NVCSI 4× PORT → 2× VI → DMA ~2.2 GiB/s @ MODE1 · 30 Hz SPI / I²C LO MASTER-MASTER LO MASTER-SLAVE (ALT.) CSI-2 / C-PHY A-PHY (1 LINK PER SUBARRAY) V4L2 · DMA
The data path in one sentence.On each subarray board the FPGA combiner merges the two AWR2243 CSI-2 streams into one 2-VC stream and a dedicated Valens VA70xx serializer packs it onto A-PHY; eight long-reach links (~15 m cable) carry everything to the deserializers at the Jetson, which hand the streams over C-PHY into the NVCSI ports — end to end without TCP, without a userspace hop.
Flexible LO domains.The master-master cascade clocks all eight subarrays; master-slave adds a second LO domain for up to four of them — enabling splits like 8/0, 7/1 or 4/3/1, with individual subarrays running autonomously.
Why C-PHY on the Jetson side?C-PHY carries ~2.28 bits per symbol — about twice the D-PHY bandwidth per pin. One 3-wire trio per lane bundle is enough, saving routing at the MIPI connector and feeding the full ~2.2 GiB/s of raw IQ without lane shortage.
03 · CHANNEL MAPPING

Every stream has an address.

A fixed, predictable mapping from subarray to device node — the same scheme at every build stage.

SUBAWR2243STM32L5LO DOMAINA-PHYV4L2
Sub 1AWR-1a · AWR-1b#1ALink 1/dev/video0 .. 1
Sub 2AWR-2a · AWR-2b#2ALink 2/dev/video2 .. 3
Sub 3AWR-3a · AWR-3b#3ALink 3/dev/video4 .. 5
Sub 4AWR-4a · AWR-4b#4ALink 4/dev/video6 .. 7
Sub 5AWR-5a · AWR-5b#5BLink 5/dev/video8 .. 9
Sub 6AWR-6a · AWR-6b#6BLink 6/dev/video10 .. 11
Sub 7AWR-7a · AWR-7b#7BLink 7/dev/video12 .. 13
Sub 8AWR-8a · AWR-8b#8BLink 8/dev/video14 .. 15

I²C addresses serve only as probe hooks (bypass_i2c=1) — the real chirp configuration reaches the AWR2243 over SPI from each board's STM32L5.

04 · COHERENCE MODES

Coherent where it counts. Autonomous where it helps.

Two cascade masters make LO distribution a configuration switch: run all eight subarrays as one aperture — or split them.

SPLIT · 8 / 0

All coherent

Cascade-Master A (master-master) clocks all eight subarrays — one cross-coherent aperture of 3072 virtual antennas.

SPLIT · 7 / 1

Seven plus one

Seven subarrays stay coherent while one runs autonomously — for example with its own chirp preset in parallel.

SPLIT · 4 / 3 / 1

Two domains plus one

Cascade-Master B (master-slave) adds a second LO domain for up to four subarrays — groups run independently, individual subarrays fully autonomous.

Capon beamforming runs strictly per subarray — the gaps between subarrays would produce grating lobes. The cross-coherent 3072-antenna aperture remains available on top for advanced processing.

05 · PERFORMANCE

Real time at full scale.

Benchmarked on the Jetson AGX Orin 64 GB — CPU pipeline first, cuFFT where it pays off.

~2.2 GiB/s
RAW IQ @ 30 HZ
25 Hz
CPU · 3072 ANT · 39 MS
~37 Hz
CUFFT · ~27 MS
<30 ms
END-TO-END LATENCY
~95 W
SYSTEM · 130 W PEAK
36.8 Gbit/s PEAK PAYLOAD 5.2× CUFFT SPEEDUP · 512×3072 BATCH FFT 71 UNIT TESTS · CUDA REL_ERROR < 1E-6 RAW12 12-BIT IQ · NOT BAYER

Modular by design.

From a single subarray to the full 8-subarray system — architecture, firmware and software scale by configuration, not redesign. We serve any configuration on request.

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